The Digital Design Engineer will be responsible for design and verification of our Video IP cores. Part of a team of top-class industry video experts, you will develop high performance Video compression and decompression IP cores in RTL supporting all video standards including HEVC / AV1 / VVC …)
BEng, MEng or MS in Electronics Engineering or related discipline.
The ideal candidate has has at least a 3-year hands-on experience with Front-End design for ASIC, video processing/coding or signal processing, , fluent English communication skills and must be a great team player.
Verilog (and/or VHDL) language proficiency, combined with excellent skills of CAD tools and ASIC design flows (modeling, design, simulation, synthesis, verification, etc.).
Knowledge of C/C ++, scripting languages and optimization of architectures and micro-architectures at HW / RTL level is required.
Understanding of video compression / decoding algorithms (for example: H.264 / H.265) is a plus.
Allegro DVT, headquartered in Grenoble (Meylan), France, is a world leading company offering digital video processing solutions including compliance streams and video codec semiconductor IPs focused on the H.264, HEVC, AVS2/3, VP9, AV1, H.266/VVC standards.
Founded in 2003, Allegro is today a recognized market leader in video compression technologies and has been a long term partner for brand name semiconductor companies worldwide.
Along with the rapid growth of our IP business, Allegro DVT is looking for ASIC Digital Design Engineers to join our engineering teams in Grenoble/France and Belfast/NI.