D310 Decoder IP

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D310 is the Allegro DVT’s ultimate multi-format, multi-stream real-time hardware decoder IP core, for all semiconductor manufacturers looking to integrate a high-performance video decoding solutions into their chips.

Built upon a true multi-format architecture, the D310 decoder IP core provides highly scalable solution up to 8K resolution through their multi-core architecture and selectable video codecs.

The D310 decoder IP core also generalizes the ultra-low latency decoding down to sub-frame latency for all mainstream video formats: AV1, VP9, H.265/HEVC, H.264/AVC and JPEG. With 8-, 10- and 12-bit support and supporting chroma sampling of 4:2:0, 4:2:2 and 4:4:4, this decoder core is truly market leading.

Key advantages :

Prefectly suited for 8K video resolutions
Selectable video codecs
Low latency decoding
Minimal silicon area
Optimized memory bandwidth
Support of compression mechanisms to lower the memory bandwidth requirements
Fast and easy SoC integration
User configurable control software

Supported formats

AV1 Main profile (4:2:0 8/10-bit) and Professional profile (4:2:2 10-bit)

VP9 Profile 0 (4:2:0 8-bit), Profile 2 (4:2:0 10-bit) and Profile 3 (4:2:2 10-bit)

H.265/HEVC Main, Main 10 and 4:2:2, 4:4:4 profiles

H.264/AVC Baseline, Main, High, 4:2:2, 4:4:4 profiles

8-bit, 10-bit, 12-bit color depth

JPEG Baseline

Interfaces

AMBA APB interface for control registers programming

AMBA AXI interfaces for data access

Deliverables

RTL source code

C control software

Bit accurate executable software reference model

Documentation

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D310 Decoder IP

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D310 Decoder IP

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